Programmable integrated circuits (ICs) are a well-known type of integrated circuit that may be programmed to perform specified logic functions. One type of programmable IC, the Field Programmable Gate Array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, Input/Output Blocks (IOBs), Configurable Logic Blocks (CLBs), dedicated Random Access Memory Blocks (BRAMs), multipliers, Digital Signal Processing blocks (DSPs), processors, clock managers, Delay Lock Loops (DLLs), Multi-Gigabit Transceivers (MGTs) and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by Programmable Interconnect Points (PIPs). The programmable logic implements the logic of a user design using programmable elements that may include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and the programmable logic are typically programmed by loading a bitstream of configuration data into internal configuration memory cells during a configuration event that defines how the programmable elements are configured. The configuration data may be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of programmable IC is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these PLDs, the functionality of the device is controlled by configuration data bits provided to the device for that purpose. The configuration data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Due to advancements in processing technology, complex integrated circuits (ICs) can be designed using various levels of abstraction. Using a hardware description language (HDL), circuits can be designed at the gate level, the register transfer level (RTL), and higher logical levels. When designing using an HDL, the designer describes the behavior of a system in terms of signals that are generated and propagated through combinatorial modules from one set of registers to another set of registers. HDLs provide a rich set of constructs to describe the functionality of each module. Modules may be combined and augmented to form even higher-level modules.
System-level integration relies on reuse of previously created designs, from either within an enterprise or from a commercial provider. Libraries of pre-developed blocks of logic have been developed that can be included in an FPGA design. Such library modules include, for example, adders, multipliers, filters, and other arithmetic and DSP functions from which system designs can be readily constructed. The engineering community sometimes refers to these previously created designs as “design modules,” “cores,” “IP cores” (intellectual property cores), or “logic cores,” and such terms are used interchangeably herein. The use of pre-developed logic cores permits faster design cycles by eliminating the redesign of circuits. Thus, using cores from a library may reduce design costs. IP cores can provide, but are not limited to, digital signal processing (DSP) functions, memories, storage elements, and math functions.
IP cores can include a predetermined set of configuration bits that program the FPGA to perform one or more functions. Some IP cores include an optimally floorplanned layout targeted to a specific family of FPGAs. Alternatively, an IP core can include source code or schematics that describe the logic and connectivity of a design. IP cores including source code may be parameterizable, i.e., allowing the user to enter parameters to activate or change certain core functionality. These cores also allow the developer to simulate the core functionality with the rest of a design for testing and debugging purposes.
High level modeling and design implementation tools, such as the System Generator for Digital Signal Processing (DSP) (SysGen), may be used to generate each core. SysGen, for example, provides a block diagram based user interface for designing and debugging complex systems such as those found in highly parameterizable and reusable cores.
Once a core is generated, it may be deployed and incorporated into larger designs that utilize the functionality provided by the core. Such cores may often be available for purchase by third parties who desire the functionality provided by the core, but don't have the time and/or resources necessary to design them.
Each core, therefore, represents valuable content that, within conventional modeling and design implementation tools, may only be protected through rudimentary means. As a result, such cores may be easily “reverse engineered” and pirated with low reverse engineering costs for use by unauthorized third parties. Relatively low reverse engineering costs are possible in part because a source transformation is generally utilized to convert the block diagram based connectivity graph to a human readable format, such as a hardware design language (HDL) format, that describes the structural connectivity. Such descriptions of structural connectivity are easily reverse engineered, which facilitates unauthorized usage by third parties.
One or more embodiments of the present invention may address one or more of the above issues.